Zero-cost MTP high density NVM modules in a CMOS process flow

A. Atrash*, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64bit to 64kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18um CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10k program/erase cycles and 10year data retention at 150°C is demonstrated.

Original languageEnglish
Title of host publication2010 IEEE International Memory Workshop, IMW 2010
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 IEEE International Memory Workshop, IMW 2010 - Seoul, Korea, Republic of
Duration: 16 May 201019 May 2010

Publication series

Name2010 IEEE International Memory Workshop, IMW 2010

Conference

Conference2010 IEEE International Memory Workshop, IMW 2010
Country/TerritoryKorea, Republic of
CitySeoul
Period16/05/1019/05/10

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