X-band to W-band frequency multiplier in 65 nm CMOS process

A compact single chip x9 frequency multiplier from X band to W band implemented in 65 nm CMOS is presented. A chain of five transformer coupled stages is used, including two triplers, realized with differential common source amplifiers at class-C mode. The circuit reaches saturated output power of -3.2 dBm at 91.8 GHz with a 7.2% bandwidth from 88.9 to 95.5 GHz. The suppression of unwanted harmonics is better than 16 dBc across the bandwidth. The core design occupies 246 μ m × 706 μ m and consumes 120 mW from a 1.2 V supply. Supply voltage increase to 1.3 V yields a peak output power of -2.7 dBm and 160 mW of dc power.