What Cannot Be Implemented on Weak Memory?

Armando Castañeda*, Gregory Chockler*, Brijesh Dongol*, Ori Lahav*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We present a general methodology for establishing the impossibility of implementing certain concurrent objects on different (weak) memory models. The key idea behind our approach lies in characterizing memory models by their mergeability properties, identifying restrictions under which independent memory traces can be merged into a single valid memory trace. In turn, we show that the mergeability properties of the underlying memory model entail similar mergeability requirements on the specifications of objects that can be implemented on that memory model. We demonstrate the applicability of our approach to establish the impossibility of implementing standard distributed objects with different restrictions on memory traces on three memory models: strictly consistent memory, total store order, and release-acquire. These impossibility results allow us to identify tight and almost tight bounds for some objects, as well as new separation results between weak memory models, and between well-studied objects based on their implementability on weak memory models.

Original languageEnglish
Title of host publication38th International Symposium on Distributed Computing, DISC 2024
EditorsDan Alistarh
PublisherSchloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing
ISBN (Electronic)9783959773522
DOIs
StatePublished - 24 Oct 2024
Event38th International Symposium on Distributed Computing, DISC 2024 - Madrid, Spain
Duration: 28 Oct 20241 Nov 2024

Publication series

NameLeibniz International Proceedings in Informatics, LIPIcs
Volume319
ISSN (Print)1868-8969

Conference

Conference38th International Symposium on Distributed Computing, DISC 2024
Country/TerritorySpain
CityMadrid
Period28/10/241/11/24

Keywords

  • Impossibility
  • Release-Acquire
  • Total-Store Order
  • Weak Memory Models

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