TY - GEN
T1 - Unleashing SmartNIC Packet Processing Performance in P4
AU - Xing, Jiarong
AU - Qiu, Yiming
AU - Hsu, Kuo Feng
AU - Sui, Songyuan
AU - Manaa, Khalid
AU - Shabtai, Omer
AU - Piasetzky, Yonatan
AU - Kadosh, Matty
AU - Krishnamurthy, Arvind
AU - Ng, T. S.Eugene
AU - Chen, Ang
N1 - Publisher Copyright:
© 2023 ACM.
PY - 2023/9/10
Y1 - 2023/9/10
N2 - SmartNICs are on the rise as a packet processing platform, with the trend towards a uniform P4 programming model. However, unleashing SmartNIC packet processing performance in P4 is a formidable task. Traditional SmartNIC optimizations rely on low-level program tuning, but P4 abstractions operate at one level above. At the same time, today's P4 optimizations primarily focus on resource packing rather than performance tuning. We develop Pipeleon, an automated performance optimization framework for P4 programmable SmartNICs. We introduce techniques that are tailored to the performance characteristics of SmartNICs, and further leverage dynamic workload patterns for profile-guided optimization. Pipeleon pinpoints program hotspots at the P4 level and computes runtime optimization plans to specialize the program layout based on the latest profile. We have prototyped Pipeleon and applied it to optimize two popular P4 SmartNICs - -Nvidia BlueField2 and Netronome Agilio CX - -as well as a software SmartNIC emulator extended based on BMv2. Our results show that Pipeleon significantly improves SmartNIC packet processing performance in realistic scenarios.
AB - SmartNICs are on the rise as a packet processing platform, with the trend towards a uniform P4 programming model. However, unleashing SmartNIC packet processing performance in P4 is a formidable task. Traditional SmartNIC optimizations rely on low-level program tuning, but P4 abstractions operate at one level above. At the same time, today's P4 optimizations primarily focus on resource packing rather than performance tuning. We develop Pipeleon, an automated performance optimization framework for P4 programmable SmartNICs. We introduce techniques that are tailored to the performance characteristics of SmartNICs, and further leverage dynamic workload patterns for profile-guided optimization. Pipeleon pinpoints program hotspots at the P4 level and computes runtime optimization plans to specialize the program layout based on the latest profile. We have prototyped Pipeleon and applied it to optimize two popular P4 SmartNICs - -Nvidia BlueField2 and Netronome Agilio CX - -as well as a software SmartNIC emulator extended based on BMv2. Our results show that Pipeleon significantly improves SmartNIC packet processing performance in realistic scenarios.
KW - P4
KW - SmartNICs
KW - runtime program optimization
UR - http://www.scopus.com/inward/record.url?scp=85174008350&partnerID=8YFLogxK
U2 - 10.1145/3603269.3604882
DO - 10.1145/3603269.3604882
M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???
AN - SCOPUS:85174008350
T3 - SIGCOMM 2023 - Proceedings of the ACM SIGCOMM 2023 Conference
SP - 1028
EP - 1042
BT - SIGCOMM 2023 - Proceedings of the ACM SIGCOMM 2023 Conference
PB - Association for Computing Machinery, Inc
T2 - ACM SIGCOMM 2023 Conference
Y2 - 10 September 2023 through 14 September 2023
ER -