Understanding tradeoffs in software transactional memory

Dave Dice*, Nir Shavit

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

There has been a flurry of recent work on the design of high performance software and hybrid hardware/software transactional memories (STMs and HyTMs). This paper reexamines the design decisions behind several of these stateof-the-art algorithms, adopting some ideas, rejecting others, all in an attempt to make STMs faster. We created the transactional locking (TL) framework of STM algorithms and used it to conduct a range of comparisons of the performance of non-blocking, lock-based, and Hybrid STM algorithms versus fine-grained hand-crafted ones. We were able to make several illuminating observations regarding lock acquisition order, the interaction of STMs with memory management schemes, and the role of overheads and abort rates in STM performance.

Original languageEnglish
Title of host publicationInternational Symposium on Code Generation and Optimization, CGO 2007
Pages21-33
Number of pages13
DOIs
StatePublished - 2007
EventInternational Symposium on Code Generation and Optimization, CGO 2007 - San Jose, CA, United States
Duration: 11 Mar 200714 Mar 2007

Publication series

NameInternational Symposium on Code Generation and Optimization, CGO 2007

Conference

ConferenceInternational Symposium on Code Generation and Optimization, CGO 2007
Country/TerritoryUnited States
CitySan Jose, CA
Period11/03/0714/03/07

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