The nature of HT Vt shift in NROM memory transistors

David Fuks*, Arnold Kiv, Yakov Roizin, Micha Gutman, Rachel Avichail-Bibi, Tatyana Maximova

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Physical mechanisms of Vt shift in NROM (micro FLASH) memory transistorsmicroFLASH memory is the trademark of Tower Semiconductor Ltd. microFLASH is based on the NROM technology. NROM is the trademark of Saifun Semiconductor Ltd. after cycling are considered. Computer simulation is combined with analytical description of kinetics of "fast" Vt shift after cycling. The distinguishing feature of the developed model is its consistency with the positions of trapped charges obtained from charge pumping measurements and account for Coulomb correlation effects in the dynamics of injected charges in ONO. Accumulation of residual electrons and holes in the injection region and electrons trapped far from the drain is accounted in the model. Two main processes during the cycling determine the further HT Vt shift: the first one is caused by Coulomb repulsion of injected electrons, and another one is linked to the trapping and re-trapping of electrons. The dependence of "fast" Vt shift on the number of cycles is obtained and verified by experimental data. The approach can be used to predict the behavior of Vt during the long-term exploitation of memory devices that experienced up to 10 k program/erase cycles.

Original languageEnglish
Pages (from-to)304-313
Number of pages10
JournalIEEE Transactions on Electron Devices
Issue number2
StatePublished - Feb 2006
Externally publishedYes


  • NROM
  • Nonvolatile memory (NVM) transistors
  • Reliability modeling
  • Semiconductor memories
  • Trapping


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