TY - JOUR
T1 - The nature of HT Vt shift in NROM memory transistors
AU - Fuks, David
AU - Kiv, Arnold
AU - Roizin, Yakov
AU - Gutman, Micha
AU - Avichail-Bibi, Rachel
AU - Maximova, Tatyana
N1 - Funding Information:
Manuscript received November 11, 2004; revised September 6, 2005. This work was supported by the MAGNET program of the Chief Scientist Office at the Israeli Ministry of Industry and Trade, Consortium “Emerging Dielectrics and Conductor Technologies.” The review of this paper was arranged by Editor R. Shrivastava.
PY - 2006/2
Y1 - 2006/2
N2 - Physical mechanisms of Vt shift in NROM (micro FLASH) memory transistorsmicroFLASH memory is the trademark of Tower Semiconductor Ltd. microFLASH is based on the NROM technology. NROM is the trademark of Saifun Semiconductor Ltd. after cycling are considered. Computer simulation is combined with analytical description of kinetics of "fast" Vt shift after cycling. The distinguishing feature of the developed model is its consistency with the positions of trapped charges obtained from charge pumping measurements and account for Coulomb correlation effects in the dynamics of injected charges in ONO. Accumulation of residual electrons and holes in the injection region and electrons trapped far from the drain is accounted in the model. Two main processes during the cycling determine the further HT Vt shift: the first one is caused by Coulomb repulsion of injected electrons, and another one is linked to the trapping and re-trapping of electrons. The dependence of "fast" Vt shift on the number of cycles is obtained and verified by experimental data. The approach can be used to predict the behavior of Vt during the long-term exploitation of memory devices that experienced up to 10 k program/erase cycles.
AB - Physical mechanisms of Vt shift in NROM (micro FLASH) memory transistorsmicroFLASH memory is the trademark of Tower Semiconductor Ltd. microFLASH is based on the NROM technology. NROM is the trademark of Saifun Semiconductor Ltd. after cycling are considered. Computer simulation is combined with analytical description of kinetics of "fast" Vt shift after cycling. The distinguishing feature of the developed model is its consistency with the positions of trapped charges obtained from charge pumping measurements and account for Coulomb correlation effects in the dynamics of injected charges in ONO. Accumulation of residual electrons and holes in the injection region and electrons trapped far from the drain is accounted in the model. Two main processes during the cycling determine the further HT Vt shift: the first one is caused by Coulomb repulsion of injected electrons, and another one is linked to the trapping and re-trapping of electrons. The dependence of "fast" Vt shift on the number of cycles is obtained and verified by experimental data. The approach can be used to predict the behavior of Vt during the long-term exploitation of memory devices that experienced up to 10 k program/erase cycles.
KW - NROM
KW - Nonvolatile memory (NVM) transistors
KW - Reliability modeling
KW - Semiconductor memories
KW - Trapping
UR - http://www.scopus.com/inward/record.url?scp=31744451477&partnerID=8YFLogxK
U2 - 10.1109/TED.2005.862236
DO - 10.1109/TED.2005.862236
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AN - SCOPUS:31744451477
SN - 0018-9383
VL - 53
SP - 304
EP - 313
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 2
ER -