Taming release-acquire consistency

Ori Lahav, Nick Giannarakis, Viktor Vafeiadis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

49 Scopus citations

Abstract

We introduce a strengthening of the release-acquire fragment of the C11 memory model that (i) forbids dubious behaviors that are not observed in any implementation; (ii) supports fence instructions that restore sequential consistency; and (iii) admits an equivalent intuitive operational semantics based on point-to-point communication. This strengthening has no additional implementation cost: it allows the same local optimizations as C11 release and acquire accesses, and has exactly the same compilation schemes to the x86- TSO and Power architectures. In fact, the compilation to Power is complete with respect to a recent axiomatic model of Power; that is, the compiled program exhibits exactly the same behaviors as the source one. Moreover, we provide criteria for placing enough fence instructions to ensure sequential consistency, and apply them to an efficient RCU implementation.

Original languageEnglish
Title of host publicationPOPL 2016 - Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
EditorsRupak Majumdar, Rastislav Bodik
PublisherAssociation for Computing Machinery
Pages649-662
Number of pages14
ISBN (Electronic)9781450335492
DOIs
StatePublished - 11 Jan 2016
Externally publishedYes
Event43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2016 - St. Petersburg, United States
Duration: 20 Jan 201622 Jan 2016

Publication series

NameConference Record of the Annual ACM Symposium on Principles of Programming Languages
Volume20-22-January-2016
ISSN (Print)0730-8566

Conference

Conference43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2016
Country/TerritoryUnited States
CitySt. Petersburg
Period20/01/1622/01/16

Keywords

  • C11
  • Operational semantics
  • Release-acquire
  • Weak memory model

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