Systolic architecture for performing cross-section on binary linear codes

Summary form only given, as follows. Let C[n, k] be a binary linear code of blocklength n and dimension k. Performing cross-section on the generator matrix of the code G by a codeword a = (a₁, a₂, ... a_n) ε C is computing a k' x n generator matrix G' of the shortened subcode of C consisting of all the codewords c = (c₁, c₂, ... c_n) ε C, such that c_i = 0 whenever a_i = 1. It was shown by Be'ery and Snyders that soft-decision decoding complexity of binary linear codes may be exponentially reduced by using zero-concurring codewords in the decoding procedure. Several optimal and suboptimal algorithms for the search of such codewords were recently presented by the authors. The optimal algorithms can be essentially reduced to repetitive execution of the same operation, namely performing cross-section on the generator matrix of the code. Systolic architecture for this purpose, i.e. a two-dimensional n × n systolic array, has been designed. It consists of two types of simple processor elements, operating synchronously. Cross-section by an arbitrary codeword is performed in k + 1 cycles. The delay of the systolic array is n cycles. The average speed-up factor relative to a single one-bit processor is n²/2 and the efficiency is 1/2.