Survivable self-checking sequential circuits

I. Levin; A. Matrosova; S. Ostanin

doi:10.1109/DFTVS.2001.966793

Survivable self-checking sequential circuits

I. Levin, A. Matrosova, S. Ostanin

School of Education

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

Original language	English
Pages (from-to)	395-402
Number of pages	8
Journal	IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFTVS.2001.966793
State	Published - 2001

Access to Document

10.1109/DFTVS.2001.966793

Cite this

@article{18185472c33e4314948ac79796ad3010,

title = "Survivable self-checking sequential circuits",

abstract = "This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.",

author = "I. Levin and A. Matrosova and S. Ostanin",

year = "2001",

doi = "10.1109/DFTVS.2001.966793",

language = "אנגלית",

pages = "395--402",

journal = "IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems",

issn = "1063-6722",

}

TY - JOUR

T1 - Survivable self-checking sequential circuits

AU - Levin, I.

AU - Matrosova, A.

AU - Ostanin, S.

PY - 2001

Y1 - 2001

N2 - This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

AB - This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

UR - http://www.scopus.com/inward/record.url?scp=0035201981&partnerID=8YFLogxK

U2 - 10.1109/DFTVS.2001.966793

DO - 10.1109/DFTVS.2001.966793

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:0035201981

SN - 1063-6722

SP - 395

EP - 402

JO - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

JF - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

ER -

Survivable self-checking sequential circuits

Abstract

Access to Document

Other files and links

Fingerprint

Cite this