Abstract
In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature Vt drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature Vt drift is significantly decreased by using bottom oxide (BOX) with the thickness TBOX < 50 Å. Excellent retention properties are preserved for TBOX up to 33 Å. The results of single-cell studies were confirmed on 2 Mb memory arrays that underwent up to 1000 program/ erase cycles. Peculiarities of hole injection into the nitride of oxide-nitride-oxide in the erase operation are considered for explanation of the observed results. The improvement is associated with a lesser amount of holes used in the erase.
Original language | English |
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Pages (from-to) | 35-37 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 26 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2005 |
Externally published | Yes |
Keywords
- NROM
- Oxide-nitride-oxide (ONO)
- Reliability
- Silicon-oxide-nitride-oxide-silicon (SONOS) memory