Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices

An analytical model is presented for the subthreshold slope degradation of localized-charge-trapping based non-volatile memory devices. The model incorporates fringing field effects and asserts that the subthreshold slope degradation is a distinct characteristic of localized-charge-trapping. Results are compared with experimental data and two-dimensional simulations performed on an NROM™ non-volatile memory cell. These substantiate that generation of interface states is not the primary cause of the discussed phenomenon and indicate that channel-hot-electron injection takes place mostly in a narrow region at the drain junction, with a ∼20 nm tail above the transistor channel. This implies that the localization concept does not impair the scalability of NROM™, two physical bits per cell, technology.