Two compilation techniques for enhancing scalar performance in high-speed scientific processor are studied, namely software pipelining and loop unrolling. The impact of the architecture (size of the register file) and of the hardware (size of instruction buffer) on the efficiency of loop unrolling is examined. A methodology for classifying software pipelining techniques is developed. For loop unrolling, a straightforward scheduling algorithm is shown to produce near-optimal results when not inhibited by recurrences or memory hazards. Software pipelining requires less hardware but also achieves less speedup. It is shown that the performance produced with a modified CRAY-1S scalar architecture and a code scheduler utilizing loop unrolling is comparable to the performance achieved by the CRAY-1S with a vector unit and the CFT vectorizing Fortran compiler.
|Title of host publication||Unknown Host Publication Title|
|Number of pages||5|
|State||Published - 1987|