Streamlined network-on-chip for multicore embedded architectures

Gadi Oxman*, Shlomo Weiss, Yitzhak Birk

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations


MPSoCs are becoming complex systems incorporating a large number of compute cores as well as various accelerators and application specific units. To handle the communication in MPSoCs, the Network-on-Chip (NoC) concept has been proposed as a versatile and scalable solution. The cost of the communication subsystem may have a major impact on the overall cost of the SoC; hence the need for careful evaluation of NoC design alternatives. Deflection routing, characterized by router simplicity and minimal resources, is an attractive design alternative but is generally viewed as suitable only for NoC with low and medium traffic. In this paper, we propose prioritization and buffering algorithms which improve deflection routing performance to the point it becomes attractive in heavily loaded NoC as well.

Original languageEnglish
Title of host publicationArchitecture of Computing Systems, ARCS 2012 - 25th International Conference, Proceedings
Number of pages12
StatePublished - 2012
Event25th International Conference on Architecture of Computing Systems, ARCS 2012 - Munich, Germany
Duration: 28 Feb 20122 Mar 2012

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7179 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference25th International Conference on Architecture of Computing Systems, ARCS 2012


  • MPSoC
  • Multicore embedded systems
  • NoC
  • deflection routing
  • network-on-chip


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