SiO2Si3N4Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

M. Lisiansky, A. Heiman, M. Kovler, A. Fenigstein, Y. Roizin, I. Levin, A. Gladkikh, M. Oksman, R. Edrei, A. Hoffman, Y. Shnieder, T. Claasen

Research output: Contribution to journalArticlepeer-review

Abstract

Effects of interfaces and thermal annealing on the electrical performance of the Si O2 Si3 N4 Al2 O3 (ONA) stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si3 N4 Al2 O3 and Al2 O3 /metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al2 O3 growth, a high-temperature annealing of the ONA stack in the N2 + O2 atmosphere, and a metal gate electrode having a high work function (Pt). These devices exhibited electrical performance superior to that of their existing Si O2 Si3 N4 Si O2 analogs.

Original languageEnglish
Article number153506
JournalApplied Physics Letters
Volume89
Issue number15
DOIs
StatePublished - 2006
Externally publishedYes

Fingerprint

Dive into the research topics of 'SiO2Si3N4Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing'. Together they form a unique fingerprint.

Cite this