SiMT-DSP: A massively multithreaded DSP architecture

Ben Perach, Shlomo Weiss*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Processor designers attempt to gain performance by introducing new, more efficient architectures. Digital signal processors (DSPs) are designed to process very efficiently digital signal applications. This focus allows DSP designers to select tradeoffs that may not be appropriate for general purpose processors. For example, the typical power consumption of DSPs is measured in milliwatts, while the power used by an Intel state-of-the-art processor is in the range of tens of watts. In recent years, we have seen a growing use of graphics processor units (GPUs) by nongraphical scientific applications because of their computation capabilities. In this paper, we introduce a new DSP architecture designed on the basis of the same parallel processing principles used in GPU architectures. We implement this new architecture on field-programmable gate array, show evaluation results for widely used DSP algorithms, and evaluate die area and power consumption. We achieve similar computation speeds as in GPUs with an evaluated die area of 9.88 mm2 and evaluated power consumption of 2.273 W due to the use of hardware adaptations for DSP applications.

Original languageEnglish
Pages (from-to)1413-1426
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume26
Issue number8
DOIs
StatePublished - Aug 2018

Keywords

  • Digital signal processor (DSP)
  • multithreaded
  • processor architecture

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