Shallow multiplication circuits

Michael S. Paterson, Uri Zwick

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Y. Ofman (1963), C. S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.

Original languageEnglish
Title of host publicationProceedings - Symposium on Computer Arithmetic
PublisherPubl by IEEE
Pages28-34
Number of pages7
ISBN (Print)0818691514
StatePublished - Jun 1991
Externally publishedYes
EventProceedings of the 10th IEEE Symposium on Computer Arithmetic - Grenoble, Fr
Duration: 26 Jun 199128 Jun 1991

Publication series

NameProceedings - Symposium on Computer Arithmetic

Conference

ConferenceProceedings of the 10th IEEE Symposium on Computer Arithmetic
CityGrenoble, Fr
Period26/06/9128/06/91

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