TY - GEN

T1 - Shallow multiplication circuits

AU - Paterson, Michael S.

AU - Zwick, Uri

PY - 1991/6

Y1 - 1991/6

N2 - Y. Ofman (1963), C. S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.

AB - Y. Ofman (1963), C. S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.

UR - http://www.scopus.com/inward/record.url?scp=0026169920&partnerID=8YFLogxK

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AN - SCOPUS:0026169920

SN - 0818691514

T3 - Proceedings - Symposium on Computer Arithmetic

SP - 28

EP - 34

BT - Proceedings - Symposium on Computer Arithmetic

PB - Publ by IEEE

T2 - Proceedings of the 10th IEEE Symposium on Computer Arithmetic

Y2 - 26 June 1991 through 28 June 1991

ER -