## Abstract

A theory is developed for the construction of carry-save networks with minimal delay, using a given collection of carry-save adders each of which may receive inputs and produce outputs using several different representation standards. The construction of some new carry-save adders is described. Using these carry-save adders optimally, as prescribed by the above theory, we get {∧, ∨, ⊕}-circuits of depth 3.48 log_{2}n and {∧, ∨, {bottom left crop}}-circuits of depth 4.95 log_{2}n for the carry-save addition of n numbers of arbitrary length. As a consequence we get multiplication circuits of the same depth. These circuits put out two numbers whose sum is the result of the multiplication. If a single output number is required then the depth of the multiplication circuits increases respectively to 4.48 log_{2}n and 5.95 log_{2}n. We also get {∧, ⊕, {bottom left crop}}-formulae of size O (n^{3.13}) and {∧, {bottom left crop}}-formulae of size O (n^{4.57}) for all the output bits of a carry-save addition of n numbers. As a consequence we get formulae of the same size for the majority function and many other symmetric Boolean functions.

Original language | English |
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Pages (from-to) | 262-291 |

Number of pages | 30 |

Journal | Computational Complexity |

Volume | 3 |

Issue number | 3 |

DOIs | |

State | Published - Sep 1993 |

## Keywords

- Multiplication
- Subject classifications: 68Q25, 06E30, 94C10
- carry-save addition
- circuits
- formulae