Shallow circuits and concise formulae for multiple addition and multiplication

Michael Paterson*, Uri Zwick

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


A theory is developed for the construction of carry-save networks with minimal delay, using a given collection of carry-save adders each of which may receive inputs and produce outputs using several different representation standards. The construction of some new carry-save adders is described. Using these carry-save adders optimally, as prescribed by the above theory, we get {∧, ∨, ⊕}-circuits of depth 3.48 log2n and {∧, ∨, {bottom left crop}}-circuits of depth 4.95 log2n for the carry-save addition of n numbers of arbitrary length. As a consequence we get multiplication circuits of the same depth. These circuits put out two numbers whose sum is the result of the multiplication. If a single output number is required then the depth of the multiplication circuits increases respectively to 4.48 log2n and 5.95 log2n. We also get {∧, ⊕, {bottom left crop}}-formulae of size O (n3.13) and {∧, {bottom left crop}}-formulae of size O (n4.57) for all the output bits of a carry-save addition of n numbers. As a consequence we get formulae of the same size for the majority function and many other symmetric Boolean functions.

Original languageEnglish
Pages (from-to)262-291
Number of pages30
JournalComputational Complexity
Issue number3
StatePublished - Sep 1993


  • Multiplication
  • Subject classifications: 68Q25, 06E30, 94C10
  • carry-save addition
  • circuits
  • formulae


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