A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLAu realization of FSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLAu realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self-checking one with low overhead is discussed.