SDNoC: Software defined network on a chip

Konstantin Berestizshevsky, Guy Even, Yaniv Fais, Jonatan Ostrometzky

Research output: Contribution to journalArticlepeer-review

Abstract

We present a novel network-on-chip (NoC) architecture, called SDNoC, that is based on a hybrid hardware/software approach. This approach is based on a few principles used in Software defined networks (SDNs). In particular, the control network and the data network are physically separated. In addition, SDNoC is controlled by a centralized network manager (NM) implemented in software that is executed on a dedicated core. These principles lead to many advantages. 1) Computation of paths is simple and the allocation of routes is efficient because the NM has a global view. Moreover, the NM is not limited to a small set of allowed routes and can easily deal with unexpected irregular traffic patterns. 2) The switches that forward phits in SDNoC are simple because they are configured by the NM, do not store phits, and do not have routing tables. 3) The overhead consumed by packet headers/trailers and control messages is greatly reduced. 4) There is no need for a complicated error-prone distributed protocol that avoids deadlock, starvation, etc. 5) Power consumption is proportional to the traffic in the NoC (as the NM processes requests, and the switches forward incoming phits). 6) Flexible design of the NM in software facilitates the addition of features such as security and support of priorities and deadlines for Quality-of-Service (QoS).

Original languageEnglish
Pages (from-to)138-153
Number of pages16
JournalMicroprocessors and Microsystems
Volume50
DOIs
StatePublished - 1 May 2017

Keywords

  • Multi-core processing
  • Network-on-chip
  • Parallel architectures
  • Routing

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