TY - JOUR
T1 - SDNoC
T2 - Software defined network on a chip
AU - Berestizshevsky, Konstantin
AU - Even, Guy
AU - Fais, Yaniv
AU - Ostrometzky, Jonatan
N1 - Publisher Copyright:
© 2017 Elsevier B.V.
PY - 2017/5/1
Y1 - 2017/5/1
N2 - We present a novel network-on-chip (NoC) architecture, called SDNoC, that is based on a hybrid hardware/software approach. This approach is based on a few principles used in Software defined networks (SDNs). In particular, the control network and the data network are physically separated. In addition, SDNoC is controlled by a centralized network manager (NM) implemented in software that is executed on a dedicated core. These principles lead to many advantages. 1) Computation of paths is simple and the allocation of routes is efficient because the NM has a global view. Moreover, the NM is not limited to a small set of allowed routes and can easily deal with unexpected irregular traffic patterns. 2) The switches that forward phits in SDNoC are simple because they are configured by the NM, do not store phits, and do not have routing tables. 3) The overhead consumed by packet headers/trailers and control messages is greatly reduced. 4) There is no need for a complicated error-prone distributed protocol that avoids deadlock, starvation, etc. 5) Power consumption is proportional to the traffic in the NoC (as the NM processes requests, and the switches forward incoming phits). 6) Flexible design of the NM in software facilitates the addition of features such as security and support of priorities and deadlines for Quality-of-Service (QoS).
AB - We present a novel network-on-chip (NoC) architecture, called SDNoC, that is based on a hybrid hardware/software approach. This approach is based on a few principles used in Software defined networks (SDNs). In particular, the control network and the data network are physically separated. In addition, SDNoC is controlled by a centralized network manager (NM) implemented in software that is executed on a dedicated core. These principles lead to many advantages. 1) Computation of paths is simple and the allocation of routes is efficient because the NM has a global view. Moreover, the NM is not limited to a small set of allowed routes and can easily deal with unexpected irregular traffic patterns. 2) The switches that forward phits in SDNoC are simple because they are configured by the NM, do not store phits, and do not have routing tables. 3) The overhead consumed by packet headers/trailers and control messages is greatly reduced. 4) There is no need for a complicated error-prone distributed protocol that avoids deadlock, starvation, etc. 5) Power consumption is proportional to the traffic in the NoC (as the NM processes requests, and the switches forward incoming phits). 6) Flexible design of the NM in software facilitates the addition of features such as security and support of priorities and deadlines for Quality-of-Service (QoS).
KW - Multi-core processing
KW - Network-on-chip
KW - Parallel architectures
KW - Routing
UR - http://www.scopus.com/inward/record.url?scp=85015962280&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2017.03.005
DO - 10.1016/j.micpro.2017.03.005
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AN - SCOPUS:85015962280
SN - 0141-9331
VL - 50
SP - 138
EP - 153
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
ER -