Scalar Supercomputer Architecture

Shlomo Weiss*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


The focus is on high-performance scalar architectures that have the capability to issue multiple instructions per clock period. The essential characteristics and the principal architectural tradeoffs in scientific array processors, very long instruction word (VLIW) machines, the polycyclic architecture, and decoupled computers are examined. Array processors rely solely on static code scheduling done manually or by the compiler. The scheduling task is quite complex and the resulting code may not be very efficient. In a VLIW, sophisticated compiler technology provides software solutions for functions traditionally done in hardware. The polycyclic architecture is similar to array processors in its structure but provides architectural support to the instruction scheduling task. finally, in decoupled architectures the hardware changes the order of the instruction execution at run time. This dynamic code scheduling capability does not come at the expense of additional control complexity.

Original languageEnglish
Pages (from-to)1970-1982
Number of pages13
JournalProceedings of the IEEE
Issue number12
StatePublished - Dec 1989
Externally publishedYes


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