Reduction of fault latency in sequential circuits by using decomposition

Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) which describes the sequential circuit of interest, thus obtaining a number of component FSMs respectively describing the number of component circuits. Being decomposed to the number of component circuits, the initial circuit becomes able to detect faults much faster since, at each specific moment of time, one of the component circuits (FSMs) is working and all the others are being tested. The paper deals with the following aspects: a) the decomposition procedure; b) evaluation of the proposed approach based on a fault injection simulation; c) estimation of trade-off between the reduction of latency and the required hardware overhead. Results of the study are tested on a number of standard benchmarks.

Original languageEnglish
Title of host publicationProceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Pages261-269
Number of pages9
DOIs
StatePublished - 2007
Event22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 - Rome, Italy
Duration: 26 Sep 200728 Sep 2007

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Country/TerritoryItaly
CityRome
Period26/09/0728/09/07

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