Reducing leakage power with BTB access prediction

Roger Kahn, Shlomo Weiss*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper investigates three architectural methods to reduce the leakage power dissipated by the BTB data array. The first method (called here window) periodically places the entire BTB data array into drowsy mode. A drowsy entry is woken up by the first access in the time interval and remains active for the remainder of the interval (window). There is an associated performance loss which is related to the size of the window, since there is a delay when a specific line must be woken up. The second method, awake line buffer (ALB), limits the number of active BTB entries to a predetermined maximum. While this reduces power dissipation it comes with a performance penalty that is relative to the size of the buffer. ALB, however, reduces the power dissipation of the data array more than the window method. The third method, 2-level ALB (2L-ALB), uses a two level buffer with the identical number of combined entries as the previous method. This method exploits the fact that many branches operate numerous times in a fixed sequence. By predicting the next BTB access, 2L-ALB achieves further reduction in leakage power without incurring any further performance loss, compared to the ALB method.

Original languageEnglish
Pages (from-to)49-57
Number of pages9
JournalIntegration, the VLSI Journal
Volume43
Issue number1
DOIs
StatePublished - Jan 2010

Keywords

  • Branch prediction
  • Computer architecture
  • Dual voltage scaling
  • Leakage power
  • Microprocessors

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