Reconstruction of generalized Depth-3 arithmetic circuits with bounded top fan-in

Zohar S. Karnin, Amir Shpilka

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

in this paper we give reconstruction algorithms for depth-3 arithmetic circuits with k multiplication gates (also known as ∑π∑(k) circuits), where k = O(1). Namely, we give an algorithm that when given a black box holding a ∑π∑(k) circuit C over a field F as input, makes queries to the black box (possibly over a polynomial sized extension field of F) and outputs a circuit C0 computing the same polynomial as C. in particular we obtain the following results. 1) When C is a multilinear ∑π∑(k) circuit (i.e. each of its multiplication gates computes a multilinear polynomial) then our algorithm runs in polynomial time (when k is a constant) and outputs a multilinear ∑π∑(k) circuits computing the same polynomial. 2) in the general case, our algorithm runs in quasipolynomial time and outputs a generalized depth-3 circuit (as defined in [1]) with k multiplication gates. For example, the polynomials computed by generalized depth- 3 circuits can be computed by quasi-polynomial sized depth-3 circuits. in fact, our algorithm works in the slightly more general case where the black box holds a generalized depth-3 circuits. Prior to this work there were reconstruction algorithms for several different models of bounded depth circuits: the well studied class of depth-2 arithmetic circuits (that compute sparse polynomials) and its close by model of depth-3 set-multilinear circuits. For the class of depth-3 circuits only the case of k = 2 (i.e. ∑π∑(2) circuits) was known. Our proof technique combines ideas from [2] and [1] with some new ideas. Our most notable new ideas are: We prove the existence of a unique canonical representation of depth-3 circuits. This enables us to work with a specific representation in mind. Another technical contribution is an isolation lemma for depth-3 circuits that enables us to reconstruct a single multiplication gate of the circuit.

Original languageEnglish
Title of host publicationProceedings of the 2009 24th Annual IEEE Conference on Computational Complexity, CCC 2009
Pages274-285
Number of pages12
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 24th Annual IEEE Conference on Computational Complexity, CCC 2009 - Paris, France
Duration: 15 Jul 200918 Jul 2009

Publication series

NameProceedings of the Annual IEEE Conference on Computational Complexity
ISSN (Print)1093-0159

Conference

Conference2009 24th Annual IEEE Conference on Computational Complexity, CCC 2009
Country/TerritoryFrance
CityParis
Period15/07/0918/07/09

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