Power-aware out-of-order issue logic in high-performance microprocessors

Yehuda Sadeh Weinraub, Shlomo Weiss*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


The issue queue in an out-of-order execution processor is a major power consumer. We propose three methods, the last two of which are derived from the design of cache memories, to limit power dissipation by reducing the scope of the associative tag search. The first method allows tag search only in selected reservation stations. The second method replaces the CAM-based Instruction Queue with a RAM, and uses two additional structures - a table of addresses to the instruction queue and a small, fully associative buffer. In the third and final method, the table of IQ addresses is partitioned into sets, and for every access the associative search is limited to the scope of a single set. These techniques can substantially reduce the number of tag mismatches, a factor that directly affects power dissipation in CAM structures that use dissipate-on-mismatch comparators. This is achieved at the expense of little performance penalty.

Original languageEnglish
Pages (from-to)457-467
Number of pages11
JournalMicroprocessors and Microsystems
Issue number7
StatePublished - 1 Nov 2006


  • ILP
  • Issue logic
  • Out-of-order processing
  • Superscalar processors


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