POLYMORPHIC ARRAYS: AN ARCHITECTURE FOR A PROGRAMMABLE SYSTOLIC MACHINE.

The problem of designing a systolic machine layout that can accommodate rectangular process arrays while guaranteeing local communication and even load distribution is considered. Several architectures for a programmable systolic machine are evaluated, and a new 'infinite grid' architecture, termed polymorphic arrays, is described. A polymorphic array of M processors can accommodate any rectangular process-array that contains M/ ROOT 5 approximately equals 0. 4472 multiplied by (times) M processes with no more than one process per processor, and this does not depend on the aspect ratio. In addition, the process vectors 1 multiplied by M and M multiplied by 1 execute with no processor assigned more than one process. The mapping of processes to processors is continuous and consistent. It can accommodate rectangular process arrays of all aspect ratios and all sizes with the maximum load-difference between processors bounded by a constant which is a logarithmic function of M. Polymorphic arrays are actually optimal in that no other consistent assignment of processes to processors can improve the bound of M/ ROOT 5 and the imbalance bound of log (M). A polymorphic array of arbitrary size has a two-dimensional realization in which the processor interconnection wire length is of length ROOT 8 multiplied by (times) C, where C is the width of a processor. A subset of polymorphic arrays, called regular polymorphic arrays, has a two-dimensional realization using nine local building blocks.