Performance comparison of load/store and symmetric instruction set architectures

D. Alpert, A. Averbuch, O. Danieli

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Two pipeline models, one implementing a load/store architecture, the other a symmetric architecture, are compared under identical simulation environments. The symmetric architecture instructions are more powerful, but also more complex; therefore the pipeline model for the symmetric architecture contains an additional stage with an additional adder, more bypasses, and an extra port to the register file. The authors' simulations show that the path length of the load/store architecture is 1.12 longer than that of the symmetric architecture. Nevertheless, most of this advantage is lost because of various pipeline delays that reduce the speedup factor from 1.12 to 1.0375. The main delaying contribution is due to resource dependency (0.064 CPI) and control dependency (0.048 CPI).

Original languageEnglish
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Pages172-181
Number of pages10
ISBN (Print)0818620471, 9780818620478
DOIs
StatePublished - 1990
Externally publishedYes
EventProceedings of the 17th Annual International Symposium on Computer Architecture - Seattle, WA, USA
Duration: 28 May 199031 May 1990

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture
ISSN (Print)0149-7111

Conference

ConferenceProceedings of the 17th Annual International Symposium on Computer Architecture
CitySeattle, WA, USA
Period28/05/9031/05/90

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