TY - GEN
T1 - Performance comparison of load/store and symmetric instruction set architectures
AU - Alpert, D.
AU - Averbuch, A.
AU - Danieli, O.
PY - 1990
Y1 - 1990
N2 - Two pipeline models, one implementing a load/store architecture, the other a symmetric architecture, are compared under identical simulation environments. The symmetric architecture instructions are more powerful, but also more complex; therefore the pipeline model for the symmetric architecture contains an additional stage with an additional adder, more bypasses, and an extra port to the register file. The authors' simulations show that the path length of the load/store architecture is 1.12 longer than that of the symmetric architecture. Nevertheless, most of this advantage is lost because of various pipeline delays that reduce the speedup factor from 1.12 to 1.0375. The main delaying contribution is due to resource dependency (0.064 CPI) and control dependency (0.048 CPI).
AB - Two pipeline models, one implementing a load/store architecture, the other a symmetric architecture, are compared under identical simulation environments. The symmetric architecture instructions are more powerful, but also more complex; therefore the pipeline model for the symmetric architecture contains an additional stage with an additional adder, more bypasses, and an extra port to the register file. The authors' simulations show that the path length of the load/store architecture is 1.12 longer than that of the symmetric architecture. Nevertheless, most of this advantage is lost because of various pipeline delays that reduce the speedup factor from 1.12 to 1.0375. The main delaying contribution is due to resource dependency (0.064 CPI) and control dependency (0.048 CPI).
UR - http://www.scopus.com/inward/record.url?scp=0025431399&partnerID=8YFLogxK
U2 - 10.1145/325164.325137
DO - 10.1145/325164.325137
M3 - פרסום בספר כנס
AN - SCOPUS:0025431399
SN - 0818620471
SN - 9780818620478
T3 - Conference Proceedings - Annual Symposium on Computer Architecture
SP - 172
EP - 181
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - Publ by IEEE
Y2 - 28 May 1990 through 31 May 1990
ER -