PCI interface implementation using CPLD and FPGA devices

Ehud Finkelstein*, Shlomo Weiss

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Designing a PCI target or master interface using a CPLD or an FPGA requires special attention to the architectural details of the chip used. This paper reviews typical CPLD and FPGA architectural features relevant to implementations of PCI interfaces. We show different methods for implementing certain aspects of PCI interfaces using a minimal amount of chip resources, while staying compliant with the PCI standard. We discuss specific characteristics of CPLD devices as well as their limitations. Some techniques to make optimum use of CPLDs in terms of density are also discussed.

Original languageEnglish
Pages1284-1288
Number of pages5
StatePublished - 1998
EventProceedings of the 1998 9th Mediterranean Electrotechnical Conference, MELECON. Part 2 (of 2) - Tel-Aviv, Israel
Duration: 18 May 199820 May 1998

Conference

ConferenceProceedings of the 1998 9th Mediterranean Electrotechnical Conference, MELECON. Part 2 (of 2)
CityTel-Aviv, Israel
Period18/05/9820/05/98

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