Abstract
We describe the design and implementation of a highly optimized, multithreaded algorithm for the propositional satisfiability problem. The algorithm is based on the Davis-Putnam-Logemann-Loveland sequential algorithm, but includes many of the optimization techniques introduced in recent years. We provide experimental results for the execution of the parallel algorithm on a variety of multiprocessor machines with shared memory architecture. In particular, the detrimental effect of parallel execution on the performance of processor cache is studied.
Original language | English |
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Pages (from-to) | 75-90 |
Number of pages | 16 |
Journal | Electronic Notes in Theoretical Computer Science |
Volume | 128 |
Issue number | 3 |
DOIs | |
State | Published - 19 Apr 2005 |
Event | Proceedings of the 3rd International Workshop on Parallel Distributed Methods in Verification (PDMC 2004) - Duration: 4 Sep 2004 → 4 Sep 2004 |
Keywords
- Satisfiability parallel multithreaded DPLL cache performance