Parallel cycle-accurate SystemC kernel

As hardware designs become more and more complex, the verification process takes longer. The bottleneck of verifying the design is the long period of time it takes to run simulations and especially long meaningful tests such as full System on Chip (SoC) simulations. Although multicore processors are now widely available, most of the simulators being used in the verification process are still unable to efficiently use multicore platforms. In this research we developed and explored several techniques for efficiently distributing the design modules across multiple threads running in parallel. The focus was on implementing several approaches for parallelizing the simulator kernel and evaluating the performance of each approach. This research presents two novel techniques for improving the parallel simulator kernel: one improves the overhead of thread parallelism by exploiting hardware simulation characteristics while the other improves task threading by collecting run-time statistics out of similar simulations. The result is a shorter simulation time and higher utilization ratio of the computing resources. The implementation in the research is based on SystemCASS, which is a cycle accurate version of the SystemC simulator.