Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Noncoherent digital delay lock loops (DDLL) are suited for chip timing synchronisation in band-limited direct-sequence spread-spectrum (DSSS) demodulators. The diffusion approximation and the singular perturbation method are used in this paper to calculate the mean time to lose lock (MTLL) of the DDLL. Loop bandwidth optimisation for first order loop with severe Doppler is presented. A simple design rule for the loop bandwidth and a systematic approach for the loop threshold calculation are presented.