TY - JOUR
T1 - On the design of IEEE compliant floating point units
AU - Even, Guy
AU - Paul, Wolfgang J.
N1 - Funding Information:
We would like to thank Marc Daumas, Arno Formella, John Hauser, David Matula, Silvia Müller, Asger Nielsen, and Thomas Walle for many helpful suggestions and discussions. A preliminary version of this work appeared in the Proceedings of the 13th IEEE Symposium on Computer Arithmetic, pp. 54-63, July 1997. This work was done while Guy Even was visiting the University of the Saarland. Supported in part by Graduiertenkolleg “Effizienz und Komplexität von Algorithmen und Rechenanlagen,” Uni-versität des Saarlandes, and in part by the North Atlantic Treaty Organization under a grant awarded in 1996.
PY - 2000/5
Y1 - 2000/5
N2 - Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm.
AB - Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm.
UR - http://www.scopus.com/inward/record.url?scp=0034188008&partnerID=8YFLogxK
U2 - 10.1109/12.859536
DO - 10.1109/12.859536
M3 - מאמר
AN - SCOPUS:0034188008
VL - 49
SP - 398
EP - 413
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
SN - 0018-9340
IS - 5
ER -