On the design of fast IEEE floating-point adders

Keyphrases

• Logic Level 100%
• Floating-point Adder 100%
• IEEE Floating Point 100%
• Latency 50%
• Adder Design 50%
• Two-path 25%
• 2-stage 25%
• Optimization Methods 25%
• Double Precision 25%
• Leading Zero 25%
• Approximate Counting 25%
• One's Complement Subtraction 25%
• Rounding Algorithm 25%
• IEEE Rounding 25%
• IEEE Standards 25%
• Compound Adder 25%
• Rounding Mode 25%
• Pipeline Stages 25%
• Clock Period 25%
• Reduced Precision 25%
• Exhaustive Testing 25%
• Borrow-save 25%
• Low Latency 25%

Computer Science

• Floating Point 100%
• Logic Level 100%
• Optimization Technique 33%
• Save Representation 33%
• Rounding Algorithm 33%
• Rounding Mode 33%
• Double Precision 33%
• Pipeline Stage 33%
• Clock Period 33%
• Exhaustive Testing 33%
• Two-Level Logic 33%