Novel method for debug of electrostatic discharge protection in VLSI circuits

Sergey Sofer; Yefim Fefer; Mariana Borenshtein; Yoram Shapira

doi:10.1109/IPFA.2006.251043

Novel method for debug of electrostatic discharge protection in VLSI circuits

Sergey Sofer^*, Yefim Fefer, Mariana Borenshtein, Yoram Shapira

^*Corresponding author for this work

Department of Electrical Engineering - Physical Eng.

Freescale Semiconductor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure.

Original language	English
Title of host publication	Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Pages	265-269
Number of pages	5
DOIs	https://doi.org/10.1109/IPFA.2006.251043
State	Published - 2006
Event	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 - Singapore, Singapore Duration: 3 Jul 2006 → 7 Jul 2006

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Country/Territory	Singapore
City	Singapore
Period	3/07/06 → 7/07/06

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10.1109/IPFA.2006.251043

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Sofer, S., Fefer, Y., Borenshtein, M., & Shapira, Y. (2006). Novel method for debug of electrostatic discharge protection in VLSI circuits. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 (pp. 265-269). Article 4017068 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2006.251043

Sofer, Sergey ; Fefer, Yefim ; Borenshtein, Mariana et al. / Novel method for debug of electrostatic discharge protection in VLSI circuits. Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. pp. 265-269 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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title = "Novel method for debug of electrostatic discharge protection in VLSI circuits",

abstract = "A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure.",

author = "Sergey Sofer and Yefim Fefer and Mariana Borenshtein and Yoram Shapira",

year = "2006",

doi = "10.1109/IPFA.2006.251043",

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booktitle = "Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006",

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Sofer, S, Fefer, Y, Borenshtein, M & Shapira, Y 2006, Novel method for debug of electrostatic discharge protection in VLSI circuits. in Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006., 4017068, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 265-269, 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006, Singapore, Singapore, 3/07/06. https://doi.org/10.1109/IPFA.2006.251043

Novel method for debug of electrostatic discharge protection in VLSI circuits. / Sofer, Sergey; Fefer, Yefim; Borenshtein, Mariana et al.
Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 265-269 4017068 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Sofer S, Fefer Y, Borenshtein M, Shapira Y. Novel method for debug of electrostatic discharge protection in VLSI circuits. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 265-269. 4017068. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2006.251043

Novel method for debug of electrostatic discharge protection in VLSI circuits

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