Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance

V. Mikhelashvili, Y. Shneider, B. Meyler, G. Atiya, S. Yofis, T. Cohen-Hyams, W. D. Kaplan, M. Lisiansky, Y. Roizin, J. Salzman, G. Eisenstein

Research output: Contribution to journalArticlepeer-review

Abstract

We report on the structural and electrical characteristics of non-volatile memory (NVM) transistors and capacitors that use Pt nanocrystals (NCs) for charge storage. The transistor exhibits a memory window of 0.6 V for a sweep of ±2.5 V which increases to 11.5 V at ±10 V. The trapped charges (electron and hole) density for a ±10 V write/erase signal are 2.9 × 10 13 cm -2. At small source to drain voltages (V SD) and for delay times longer than 0.1 ms, negative differential resistance (NDR) type behavior of the transistor source to drain I SD-V SD characteristics is revealed. The physical mechanism responsible for the NDR is related to the dynamics of electron injection (by tunneling through the thin bottom oxide) and their trapping by the Pt NCs. The large storage capability and relatively low program/erase voltages as well as the use of Pt, that is a Fab friendly material, make the described NVM transistors promising for practical applications.

Original languageEnglish
Article number024319
JournalJournal of Applied Physics
Volume112
Issue number2
DOIs
StatePublished - 15 Jul 2012
Externally publishedYes

Fingerprint

Dive into the research topics of 'Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance'. Together they form a unique fingerprint.

Cite this