Near-optimal PLL design for decision-feedback carrier and timing recovery

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing, or other synchronization loops given the phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exists in modern receivers due to, for example, convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser linewidth. We provide an easy-to-use complete design sign procedure for second-order loops. We also introduce a design procedure for higher order loops for near-optimal performance. We show that using the traditional second-order loop is suboptimal when there is a delay in the loop, and also show large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay.