Modeling and design of a low-power injection-locked frequency divider in 90nm CMOS for 60GHz applications

Alex Katz*, Ofir Degani, Eran Socher

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper describes the modeling and design considerations of a low-power divide-by-two injection-locked frequency divider (ILFD) for 60GHz frequency synthesizer applications implemented in 90nm CMOS process. The paper proposes a divider's locking range model based on mixing analysis. The design uses a capacitor bank for the divider band selection and tail current injection. Measured results of the designed divider show minimum power consumption of 1.32mW and locking range 2.5GHz at an input power of 2dBm.

Original languageEnglish
Title of host publication2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers
Pages61-64
Number of pages4
DOIs
StatePublished - 2011
Event2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Phoenix, AR, United States
Duration: 16 Jan 201119 Jan 2011

Publication series

Name2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers

Conference

Conference2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011
Country/TerritoryUnited States
CityPhoenix, AR
Period16/01/1119/01/11

Keywords

  • CMOS
  • Injection-locked frequency divider (ILFD)
  • Locking range

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