Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions

Uri Yehuday, Ben Zion Bobrovsky, Jeffrey Davidson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Communications, ICC'07
Pages2888-2893
Number of pages6
DOIs
StatePublished - 2007
Event2007 IEEE International Conference on Communications, ICC'07 - Glasgow, Scotland, United Kingdom
Duration: 24 Jun 200728 Jun 2007

Publication series

NameIEEE International Conference on Communications
ISSN (Print)0536-1486

Conference

Conference2007 IEEE International Conference on Communications, ICC'07
Country/TerritoryUnited Kingdom
CityGlasgow, Scotland
Period24/06/0728/06/07

Keywords

  • Loop delay
  • Mean time to lose lock
  • PLL
  • Pade approximation
  • Phase noise

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