Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions

Uri Yehuday; Ben Zion Bobrovsky; Jeffrey Davidson

doi:10.1109/ICC.2007.480

Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions

Uri Yehuday^*, Ben Zion Bobrovsky, Jeffrey Davidson

^*Corresponding author for this work

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

Original language	English
Title of host publication	2007 IEEE International Conference on Communications, ICC'07
Pages	2888-2893
Number of pages	6
DOIs	https://doi.org/10.1109/ICC.2007.480
State	Published - 2007
Event	2007 IEEE International Conference on Communications, ICC'07 - Glasgow, Scotland, United Kingdom Duration: 24 Jun 2007 → 28 Jun 2007

Publication series

Name	IEEE International Conference on Communications
ISSN (Print)	0536-1486

Conference

Conference	2007 IEEE International Conference on Communications, ICC'07
Country/Territory	United Kingdom
City	Glasgow, Scotland
Period	24/06/07 → 28/06/07

Keywords

Loop delay
Mean time to lose lock
PLL
Pade approximation
Phase noise

Access to Document

10.1109/ICC.2007.480

Cite this

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title = "Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions",

abstract = "The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.",

keywords = "Loop delay, Mean time to lose lock, PLL, Pade approximation, Phase noise",

author = "Uri Yehuday and Bobrovsky, {Ben Zion} and Jeffrey Davidson",

year = "2007",

doi = "10.1109/ICC.2007.480",

language = "אנגלית",

isbn = "1424403537",

series = "IEEE International Conference on Communications",

pages = "2888--2893",

booktitle = "2007 IEEE International Conference on Communications, ICC'07",

note = "2007 IEEE International Conference on Communications, ICC'07 ; Conference date: 24-06-2007 Through 28-06-2007",

}

Yehuday, U, Bobrovsky, BZ & Davidson, J 2007, Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions. in 2007 IEEE International Conference on Communications, ICC'07., 4289151, IEEE International Conference on Communications, pp. 2888-2893, 2007 IEEE International Conference on Communications, ICC'07, Glasgow, Scotland, United Kingdom, 24/06/07. https://doi.org/10.1109/ICC.2007.480

Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions. / Yehuday, Uri; Bobrovsky, Ben Zion; Davidson, Jeffrey.
2007 IEEE International Conference on Communications, ICC'07. 2007. p. 2888-2893 4289151 (IEEE International Conference on Communications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Bobrovsky, Ben Zion

AU - Davidson, Jeffrey

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N2 - The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

AB - The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

KW - Loop delay

KW - Mean time to lose lock

KW - PLL

KW - Pade approximation

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Mean time to lose lock for a PLL with loop delay under thermal and phase noise conditions

Abstract

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Keywords

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