Low power branch prediction for embedded application processors

Modern embedded processors used in media and communi-cation portable devices are now required to execute com- plex applications and their performance requirements are getting close to the demands of general purpose processors. The performance-per-Watt ratio is an extremely important measure in portable devices because of their limited power capacity. Branch predictors, and especially the BTB, are among the largest on-chip SRAM structures (after caches), and therefore are primary contributors to the total system power. We propose a novel micro-architectural method re- ferred to as Shifted-Index BTB with a Set-Buffer, which re- duces both dynamic and static power. Extensive simula- tions show that up to 80% reduction in dynamic power is achieved at the cost of up to 0.64% system slowdown. 58% reduction is static power is also achieved by applying low- leakage power techniques that mesh well with the Set-Buffer design.