Abstract
On-die measurements of $V-{\rm DD}$ and $V-{\rm SS}$ voltages inside a 90-nm VLSI technology chip are presented. The results show local fluctuations in the $V-{\rm DD}$ and $V-{\rm SS}$ voltages with amplitudes that can reach, in severe cases, more than 10% of $V-{\rm DD}$. These fluctuations can distort analog signals, cause immediate logic faults, and also aggravate other reliability wear-out mechanisms. Both measurements and simulations predict the aggravation of this phenomenon for future technologies.
| Original language | English |
|---|---|
| Article number | 5153317 |
| Pages (from-to) | 476-482 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 9 |
| Issue number | 3 |
| DOIs | |
| State | Published - Sep 2009 |
Keywords
- Power-distribution network
- Reliability
- Supply-noise measurement
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