Local charge accumulation and trapping in grain boundaries of pentacene thin film transistors

S. Yogev, R. Matsubara, M. Nakamura, Y. Rosenwaks*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

We present a comprehensive Kelvin probe force microscopy study of grain boundaries in pentacene transistors with different film thicknesses in combination with current-voltage measurements and 3D electrostatics simulations. It is found that in pentacene films thinner than approximately 30 nm, holes are accumulated in the grain boundaries due to negative trapped charge at the SiO2-pentacene interface. On the other hand, in thicker films we observe hole depletion near the boundaries mainly due to positive charge trapping in the grain boundaries. The results are discussed in view of their effect on pentacene thin film transistors performance.

Original languageEnglish
Pages (from-to)1729-1735
Number of pages7
JournalOrganic Electronics
Volume11
Issue number11
DOIs
StatePublished - Nov 2010

Keywords

  • Grain boundaries
  • Hole accumulation
  • Organic thin film transistors
  • Pentacene

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