Lateral charge transport in the nitride layer of the NROM non-volatile memory device

NROM is a two bits per cell, localized charge trapping non-volatile memory device. A unique erase state threshold voltage drift in the NROM cell is presented. The research aimed to determine the origin of this phenomenon and assess the role of lateral misalignment between electrons and holes trapped in the ONO gate dielectric stack. Electrical characterizations combined with two-dimensional drift diffusion simulations and charge-tunneling theory were employed. It was found that the drift direction could be controlled by alteration of the voltages applied to the cell during erasure. Furthermore, the drift diminished with the number of program/erase cycles performed on the cell and demonstrated an insensitivity to vertical electric fields applied to the device. A lateral trap-to-trap hole-tunneling model was developed and shown to resolve the unique drift characteristics. Theories ascribing vertical charge tunneling to this phenomenon are demonstrated as inconsistent with most of these observations.