TY - GEN
T1 - Investigation of transactional memory using FPGAs
AU - Grinberg, Simon
AU - Weiss, Shlomo
PY - 2006
Y1 - 2006
N2 - The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring tliis approach yields a powerful substitute to simulation.
AB - The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring tliis approach yields a powerful substitute to simulation.
UR - http://www.scopus.com/inward/record.url?scp=50249141958&partnerID=8YFLogxK
U2 - 10.1109/EEEI.2006.321125
DO - 10.1109/EEEI.2006.321125
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AN - SCOPUS:50249141958
SN - 1424402301
SN - 9781424402304
T3 - IEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings
SP - 119
EP - 122
BT - 2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, IEEEI
T2 - 2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, IEEEI
Y2 - 15 November 2006 through 17 November 2006
ER -