Investigation of transactional memory using FPGAs

Simon Grinberg*, Shlomo Weiss

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring tliis approach yields a powerful substitute to simulation.

Original languageEnglish
Title of host publication2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, IEEEI
Pages119-122
Number of pages4
DOIs
StatePublished - 2006
Event2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, IEEEI - Eilat, Israel
Duration: 15 Nov 200617 Nov 2006

Publication series

NameIEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings

Conference

Conference2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, IEEEI
Country/TerritoryIsrael
CityEilat
Period15/11/0617/11/06

Fingerprint

Dive into the research topics of 'Investigation of transactional memory using FPGAs'. Together they form a unique fingerprint.

Cite this