Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance

Sergey Sofer, Yefim Fefer, Yoram Shapira

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design.

Original languageEnglish
Title of host publicationProceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Pages158-162
Number of pages5
DOIs
StatePublished - 2006
Event13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 - Singapore, Singapore
Duration: 3 Jul 20067 Jul 2006

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Country/TerritorySingapore
CitySingapore
Period3/07/067/07/06

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