Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance

Sergey Sofer; Yefim Fefer; Yoram Shapira

doi:10.1109/IPFA.2006.251020

Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance

Sergey Sofer^*, Yefim Fefer, Yoram Shapira

^*Corresponding author for this work

Department of Electrical Engineering - Physical Eng.

Freescale Semiconductor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design.

Original language	English
Title of host publication	Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Pages	158-162
Number of pages	5
DOIs	https://doi.org/10.1109/IPFA.2006.251020
State	Published - 2006
Event	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 - Singapore, Singapore Duration: 3 Jul 2006 → 7 Jul 2006

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Country/Territory	Singapore
City	Singapore
Period	3/07/06 → 7/07/06

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10.1109/IPFA.2006.251020

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Sofer, S., Fefer, Y., & Shapira, Y. (2006). Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 (pp. 158-162). Article 4017045 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2006.251020

Sofer, Sergey ; Fefer, Yefim ; Shapira, Yoram. / Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance. Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. pp. 158-162 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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title = "Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance",

abstract = "The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design.",

author = "Sergey Sofer and Yefim Fefer and Yoram Shapira",

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doi = "10.1109/IPFA.2006.251020",

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booktitle = "Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006",

note = "13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 ; Conference date: 03-07-2006 Through 07-07-2006",

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Sofer, S, Fefer, Y & Shapira, Y 2006, Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance. in Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006., 4017045, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 158-162, 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006, Singapore, Singapore, 3/07/06. https://doi.org/10.1109/IPFA.2006.251020

Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance. / Sofer, Sergey; Fefer, Yefim; Shapira, Yoram.
Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 158-162 4017045 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Sofer S, Fefer Y, Shapira Y. Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 158-162. 4017045. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2006.251020

Inductance considerations of on-chip interconnections for best electrostatic discharge protection performance

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