Indirect electrostatic discharge stressing mechanism in VLSI chips with multiple power supply domains

Sergey Sofer, Yefim Fefer, Yoram Shapira

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Indirect electrostatic discharge stressing of a chip with multiple isolated power domains was analyzed. The stress penetrates to the victim domain via common nets having non-negligible complex impedance and via coupling of the inter-domain parasitic capacitors and in some cases may cause chip damage. Copyright

Original languageEnglish
Title of host publicationISTFA 2006 - Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis
Pages389-392
Number of pages4
StatePublished - 2006
EventISTFA 2006 - 32nd International Symposium for Testing and Failure Analysis - Austin, TX, United States
Duration: 12 Nov 200616 Nov 2006

Publication series

NameConference Proceedings from the International Symposium for Testing and Failure Analysis
Volume2006

Conference

ConferenceISTFA 2006 - 32nd International Symposium for Testing and Failure Analysis
Country/TerritoryUnited States
CityAustin, TX
Period12/11/0616/11/06

Fingerprint

Dive into the research topics of 'Indirect electrostatic discharge stressing mechanism in VLSI chips with multiple power supply domains'. Together they form a unique fingerprint.

Cite this