Improving the memory-system performance of sparse-matrix vector multiplication

S. Toledo*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

115 Scopus citations

Abstract

Sparse-matrix vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-level parallelism and improve performance. The techniques include reordering to reduce cache misses (originally due to Das et al.), blocking to reduce load instructions, and prefetching to prevent multiple load-store units from stalling simultaneously. The techniques improve performance from about 40 MFLOPS (on a well-ordered matrix) to more than 100 MFLOPS on a 266-MFLOPS machine. The techniques are applicable to other superscalar RISC processors as well, and have improved performance on a Sun UltraSPARC™ I workstation, for example.

Original languageEnglish
Pages (from-to)711-725
Number of pages15
JournalIBM Journal of Research and Development
Volume41
Issue number6
DOIs
StatePublished - Nov 1997

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