Implementation of PCI-based systems using programmable logic

Designing a PCI target or master interface using a CPLD or an FPGA requires special attention to the architectural details of the chip used. The paper considers typical CPLD and FPGA architectural features relevant to implementations of PCI interfaces. Different methods of implementing certain aspects of PCI interfaces using a minimal amount of chip resources, while staying compliant with the PCI standard, are shown. A complete timing analysis of a CPLD device is given, along with the resulting signals paths that are compliant with the PCI timing requirements.