Implementation and bandwidth considerations in multi ported, on chip data cache

Asher Besserglick; Shlomo Weiss

Implementation and bandwidth considerations in multi ported, on chip data cache

Asher Besserglick^*, Shlomo Weiss

^*Corresponding author for this work

School of Electrical Engineering

Tel Aviv University

Research output: Contribution to conference › Paper › peer-review

Abstract

As CPU workload increases, the on-chip cache becomes a bottle-neck for data transfer. In this paper we evaluate the cache efficiency in terms of data bandwidth (BW), or the number of data accesses per cycle that a cache can handle. Four cache configurations are described and tested for the best BW performance. This paper deals not only with the type of two level cache configuration but also with the best size ratios of the two levels. Results given here are based on tests conducted with a cache simulation supporting two level cache configurations.

Original language	English
Pages	152-155
Number of pages	4
State	Published - 1996
Event	Proceedings of the 1996 19th Convention of Electrical and Electronics Engineers in Israel - Jerusalem, Isr Duration: 5 Nov 1996 → 6 Nov 1996

Conference

Conference	Proceedings of the 1996 19th Convention of Electrical and Electronics Engineers in Israel
City	Jerusalem, Isr
Period	5/11/96 → 6/11/96

Cite this

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title = "Implementation and bandwidth considerations in multi ported, on chip data cache",

abstract = "As CPU workload increases, the on-chip cache becomes a bottle-neck for data transfer. In this paper we evaluate the cache efficiency in terms of data bandwidth (BW), or the number of data accesses per cycle that a cache can handle. Four cache configurations are described and tested for the best BW performance. This paper deals not only with the type of two level cache configuration but also with the best size ratios of the two levels. Results given here are based on tests conducted with a cache simulation supporting two level cache configurations.",

author = "Asher Besserglick and Shlomo Weiss",

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AB - As CPU workload increases, the on-chip cache becomes a bottle-neck for data transfer. In this paper we evaluate the cache efficiency in terms of data bandwidth (BW), or the number of data accesses per cycle that a cache can handle. Four cache configurations are described and tested for the best BW performance. This paper deals not only with the type of two level cache configuration but also with the best size ratios of the two levels. Results given here are based on tests conducted with a cache simulation supporting two level cache configurations.

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T2 - Proceedings of the 1996 19th Convention of Electrical and Electronics Engineers in Israel

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Implementation and bandwidth considerations in multi ported, on chip data cache

Abstract

Conference

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