Implementation and analysis of path history in dynamic branch prediction schemes

S. Reches*, S. Weiss

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

In todays microprocessors, when chip density increases and more execution units with deeper pipelines are integrated into the processor, accurate branch prediction is essential for providing higher performance levels. Many recent branch predictors use branch execution history to identify repetitive branch behavior. By recording address information of recently executed branches, we can separate sequences of different branch instructions with identical execution history. The use of path history information has been recently addressed by Young and Smith [1] in static branch correlation, and by Young et el. [2] and Nair [3] in dynamic branch prediction methods. We present a method to implement path history in hardware-based branch prediction, and a comprehensive simulation study of branch prediction strategies integrating path history.

Original languageEnglish
Pages285-292
Number of pages8
DOIs
StatePublished - 1997
EventProceedings of the 1997 International Conference on Supercomputing - Vienna, Austria
Duration: 7 Jul 199711 Jul 1997

Conference

ConferenceProceedings of the 1997 International Conference on Supercomputing
CityVienna, Austria
Period7/07/9711/07/97

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