@inproceedings{352f8c71207d4ae0b8285e4c95eac4cb,
title = "Impact of impedance mismatch of on-die interconnects and logic cells on device reliability and functionality",
abstract = "The impact of impedance mismatch of on-die transmission lines and CMOS logic cells upon device reliability was studied. The experimentally obtained results from a test chip performed on a 45 nm CMOS technology process were compared with SPICE simulations. The results reveal that the impedance mismatch manifested by voltage overshooting and slowed down voltage transition may accelerate the device aging as well as lead to increased power consumption and logic faults.",
author = "Pavel Livshits and Moshe Gurfinkel and Alexander Rysin and Sergey Sofer and Yoram Shapira and Yefim Fefer",
year = "2010",
language = "אנגלית",
isbn = "9781605112183",
series = "Advanced Metallization Conference (AMC)",
pages = "223--228",
booktitle = "Advanced Metallization Conference 2009, AMC 2009",
note = "26th Advanced Metallization Conference, AMC 2009 ; Conference date: 13-10-2009 Through 15-10-2009",
}