Impact of impedance mismatch of on-die interconnects and logic cells on device reliability and functionality

Pavel Livshits, Moshe Gurfinkel, Alexander Rysin, Sergey Sofer, Yoram Shapira, Yefim Fefer

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The impact of impedance mismatch of on-die transmission lines and CMOS logic cells upon device reliability was studied. The experimentally obtained results from a test chip performed on a 45 nm CMOS technology process were compared with SPICE simulations. The results reveal that the impedance mismatch manifested by voltage overshooting and slowed down voltage transition may accelerate the device aging as well as lead to increased power consumption and logic faults.

Original languageEnglish
Title of host publicationAdvanced Metallization Conference 2009, AMC 2009
Pages223-228
Number of pages6
StatePublished - 2010
Event26th Advanced Metallization Conference, AMC 2009 - Baltimore, MD, United States
Duration: 13 Oct 200915 Oct 2009

Publication series

NameAdvanced Metallization Conference (AMC)
ISSN (Print)1540-1766

Conference

Conference26th Advanced Metallization Conference, AMC 2009
Country/TerritoryUnited States
CityBaltimore, MD
Period13/10/0915/10/09

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