Impact ionization measurements and modeling for power PHEMT

A systematic study of impact ionization in pseudo-morphic high electron mobility transistors (PHEMTs) has been carried out using temperature-dependent electrical measurements as well as modeling for optimizing the power performance of the devices through the best layout parameters. A measurement procedure makes it possible to define a safe transistor operation region is proposed. Impact ionization in the channel is parameterized by specific gate current and voltage values. Temperature-dependent measurements are shown to provide distinction between the impact ionization current and the thermionic field emission current. A methodology for defining an optimum vertical structure and a lateral layout for a given application and operational conditions is developed. Empirical models for optimum lateral layout for a power application were developed based on a statistical "Device Zoo" approach. The results point to an optimal gate-to-drain distance for minimum impact ionization current.